#ifndef __UDSF_RADAR_DACQ_C__
#define __UDSF_RADAR_DACQ_C__

#include "app.h"
/*
*   notice:
*   UDSF 同UDF编程：不可调用cstd-lib,只可调用"sdk_ifs_udk_cfg.h"、"sys_api.h"中列出的API函数。
*   UDSF文件内函数均需使用static修饰符，且UDF中以#include "udsf_xxx.c"形式引用
*/

#include "udsf_uart.c"
#include "udsf_spi.c"
#include "udsf_delay.c"
#include "udsf_rtc.c"
#include "udsf_protocol_debug.c"

static void udsf_data_acquisiton_continue(void)
{
		PREPDATA_HANDLE(); // copy range/vel win,copy multi-coefficient
		BBE_PREPINIT(paramDataPrep);       // PrepData param -> BBE REG
		RF_VENUS_INIT();
		
		uint32_t ana2_config0_rf_on  = paramANA_Venus->ana2.ana_cfg0;
		uint32_t ana2_config0_rf_off = paramANA_Venus->ana2.ana_cfg0 & (~1);

		paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_off;
		
		ANACFG_SET(&paramANA_Venus->ana2); // all on but rf
		udsf_delay_us(20); // wait pll ready
	
		paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_on;
		ana_Venus_st->ramp_cmd = VENUS_WAVE_START;       // sweep start
		ANACFG_SET(&paramANA_Venus->ana2); // rf on

		// wait dataprep end
		BBE_WAITISR(BBE_ISR_PREP_FRAME_END);
		
		RF_VENUS_DEINIT(); // sweep end
		BBE_OPGATE_DIS(BBE_GATE_PREP);//dp clock disable
		ANACFG_SET(&paramANA_Venus->ana1); //40M		
}


static uint32_t udsf_data_acquisiton_chirpsum(int predata_en,int alg0_en,int alg25_en,struct proto_data_cfg* p_frame_ctrl)
{
	if( predata_en ){
		PREPDATA_HANDLE();
	}

	#if( TEST_MODE == 300 )
	GPIO_OUTPUT_SET = 0;
	#endif
	BBE_PREPINIT(paramDataPrep);    //bbe init, 2.9us
	#if( TEST_MODE == 300 )
	GPIO_OUTPUT_SET = 1;
	#endif
	RF_VENUS_INIT(); //4.9us
	#if( TEST_MODE == 300 )
	GPIO_OUTPUT_SET = 0;
	#endif
	uint32_t ana2_config0_rf_on  = paramANA_Venus->ana2.ana_cfg0;
	uint32_t ana2_config0_rf_off = paramANA_Venus->ana2.ana_cfg0 & (~1);

	paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_off;
	ANACFG_SET(&paramANA_Venus->ana2);               // all on but rf
	
	paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_on;
	#if( TEST_MODE == 300 )
	GPIO_OUTPUT_SET = 1;
	#endif
	ana_Venus_st->ramp_cmd = VENUS_WAVE_START;       // sweep start


	BBE->ISR = BBE_ISR_RAMP_PEDGE;	         // wair for wave0-B
	while( (BBE->ISR & BBE_ISR_RAMP_PEDGE)==0 );
	#if( TEST_MODE == 300 )
	GPIO_OUTPUT_SET = 0;
	#endif
	int chirp_cnt = 0;
	do{
		ANACFG_SET(&paramANA_Venus->ana2); // rf on
		#if( TEST_MODE == 300 )
		GPIO_OUTPUT_SET = 1;
		#endif
		#if defined(TEST_RF_PW)
		while(1){
			WDT->STR = 1;
		}
		#endif

		// wait dataprep end
		BBE->OP_CLEAR=BBE_CLEAR_PREP;
		BBE_ISR_CLEAR(BBE_ISR_PREP_FRAME_END);
		BBE_WAITISR(BBE_ISR_PREP_FRAME_END);
		#if( TEST_MODE == 300 )
		GPIO_OUTPUT_SET = 0;
		#endif
		ANACFG_SET(&paramANA_Venus->ana3); // rf if off
		#if( TEST_MODE == 300 )
		GPIO_OUTPUT_SET = 1;
		#endif

		if( alg0_en ){
			P2_FFT_STEPCFG8_HANDLE((P2_FFT_CONFIG*)&paramALG->alg0,paramALG->alg0.dstInc*chirp_cnt);
		}

		if( alg25_en ){
			P2_FFT_STEPCFG8_HANDLE((P2_FFT_CONFIG*)&paramALG->alg25,paramALG->alg25.dstInc*chirp_cnt);
		}

		chirp_cnt++;
		
		if( p_frame_ctrl ){
			udsf_protocol_debug_send(0,p_frame_ctrl,-1,paramDataPrep->cycleNum,chirp_cnt,0);
		}
		
		if( paramDataPrep->cycleNum != chirp_cnt ){
			BBE->ISR = BBE_ISR_RAMP_PEDGE;	     // wait for wave0-B
			while( (BBE->ISR & BBE_ISR_RAMP_PEDGE)==0 );
		}
	}while(paramDataPrep->cycleNum != chirp_cnt);

	uint32_t ana_sta = ana_Venus_st->sys_sta0;
	#if( TEST_MODE == 300 )
	GPIO_OUTPUT_SET = 0;
	#endif
	RF_VENUS_DEINIT();
	#if( TEST_MODE == 300 )
	GPIO_OUTPUT_SET = 1;
	#endif
	BBE_OPGATE_DIS(BBE_GATE_PREP);//|BBE_GATE_P2|BBE_GATE_FFT);
	#if( TEST_MODE == 300 )
	GPIO_OUTPUT_SET = 0;
	#endif
	ANACFG_SET(&paramANA_Venus->ana1); //40M
	#if( TEST_MODE == 300 )
	GPIO_OUTPUT_SET = 1;
	#endif
	return  ((ana_sta>>6)&0x3);
}

// chirp间不关闭晶振休眠 RTC延时 适用于较小chirp间隔应用
static uint32_t udsf_data_acquisiton_chirpsum_ultra_lpw(int predata_en,int alg0_en,int alg25_en,int chirp_addtion_intv_us)
{
	if( predata_en ){
		PREPDATA_HANDLE();
	}
	BBE_PREPINIT(paramDataPrep);    //bbe init, 2.9us
	RF_VENUS_INIT(); //4.9us
			
	uint32_t ana2_config0_rf_on   = paramANA_Venus->ana2.ana_cfg0;
	uint32_t ana2_config0_rf_off  = paramANA_Venus->ana2.ana_cfg0 & (~1);

	paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_off;
	ANACFG_SET(&paramANA_Venus->ana2);  // all on but rf
	paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_on;

	#if( TEST_MODE == 300 )
	paramDataPrep->cycleNum = 2;
	GPIO_OUTPUT_SET = 0;
	#endif
	
	ana_Venus_st->ramp_cmd        = VENUS_WAVE_START;       // sweep start

	BBE->ISR             = BBE_ISR_RAMP_PEDGE;	   // wair for wave0-B
	while( (BBE->ISR & BBE_ISR_RAMP_PEDGE)==0 );
	
	int chirp_cnt = 0;
	do{
		ANACFG_SET(&paramANA_Venus->ana2); // rf on
		// wait dataprep end
		BBE->OP_CLEAR=BBE_CLEAR_PREP;
		BBE_ISR_CLEAR(BBE_ISR_PREP_FRAME_END);// dataprep在wave0-A可能已采集满 add@230608
		BBE_WAITISR(BBE_ISR_PREP_FRAME_END);
		
		if( chirp_addtion_intv_us ){
			#if( TEST_MODE == 300 )
			GPIO_OUTPUT_SET = 1;
			#endif
			
			ana_Venus_st->ramp_cmd = VENUS_WAVE_STOP; 
			ANACFG_SET(&paramANA_Venus->ana1);
			BBE_OPGATE_DIS(BBE_GATE_PREP|BBE_GATE_P2|BBE_GATE_FFT|BBE_GATE_CFAR); // bbe opgate
			
			if( TEST_MODE == 600 ){
				while(1){
					WDT->STR = 1;
				}
			}
			// start a
			udsf_rtc_set(1,chirp_addtion_intv_us>>5);
		}else{
			ANACFG_SET(&paramANA_Venus->ana3); // rf if off
		}
		
		if( alg0_en ){
			P2_FFT_STEPCFG8_HANDLE((P2_FFT_CONFIG*)&paramALG->alg0,paramALG->alg0.dstInc*chirp_cnt);
		}

		if( alg25_en ){
			P2_FFT_STEPCFG8_HANDLE((P2_FFT_CONFIG*)&paramALG->alg25,paramALG->alg25.dstInc*chirp_cnt);
		}

		chirp_cnt++;
		
		if( paramDataPrep->cycleNum != chirp_cnt ){
			if( chirp_addtion_intv_us ){
				#if( TEST_MODE == 300 )
				GPIO_OUTPUT_SET = 0;
				#endif

				SYSC->CLK_EN &= (~BBE_EN_Msk); // bbe clk disable		
				
				if( TEST_MODE == 601 ){
					while(1){
						WDT->STR = 1;
					}
				}
				uint32_t tmp = paramANA_Venus->ana4.ana_cfg0;
				paramANA_Venus->ana4.ana_cfg0 = tmp&(~(1<<16)); // clear "40M disable mask"
				ANACFG_SET(&paramANA_Venus->ana4); //40M
				paramANA_Venus->ana4.ana_cfg0 = tmp;
				SYSC->CLK_SEL = BBE_ISO_SEL_MSK | LRC_SEL_MSK;// | LRC_DIV128_MSK; // 8K

				#if( TEST_MODE == 300 )
				GPIO_OUTPUT_SET = 1;
				#endif
				// end a


				// start b
				if( TEST_MODE == 602 ){
					while(1){
						WDT->STR = 1;
					}
				}
				while ((RTC1->IRQ_CFG & 0x1ul) == 0); // wait rtc1 irq
				// end b

				#if( TEST_MODE == 300 )
				GPIO_OUTPUT_SET = 0;
				#endif
				SYSC->CLK_SEL = 0;                 //40M

				#if( TEST_MODE == 300 )
				GPIO_OUTPUT_SET = 1;
				#endif
				
				// start d
				RTC1->IRQ_CFG |= RTC_IRQ_MASK_Pos;    // rtc1 irq disable
				RTC1->IRQ_CFG |= RTC_IRQ_CLEAR_Msk;   // rtc1 irq flag clear
				SYSC->CLK_EN = SYSC->CLK_EN|BBE_EN_Msk&(~RTC1_PATTERN_SW_Msk);    // bbe_clk enable	
				SYSC->SWRST &= ~(1 << 11);  // bbe reset
				SYSC->SWRST |= (1 << 11);				
				BBE_OPGATE_DIS(BBE_GATE_PREP|BBE_GATE_P2|BBE_GATE_FFT|BBE_GATE_CFAR); // bbe opgate
				
				paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_off;
				ANACFG_SET(&paramANA_Venus->ana2);  // all on but rf
				paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_on;
				BBE_PREPINIT(paramDataPrep);                     // bbe dp init, 2.9us
				RF_VENUS_INIT();                                 // ramp init,   4.9us

				ana_Venus_st->ramp_cmd = VENUS_WAVE_START;       // ramp start
				#if( TEST_MODE == 300 )
				GPIO_OUTPUT_SET = 0;
				#endif
				// end d
				
				if( TEST_MODE == 604 ){
					while(1){
						WDT->STR = 1;
					}
				}
			}
			
			BBE->ISR = BBE_ISR_RAMP_PEDGE;	     // wait for wave0-B
			while( (BBE->ISR & BBE_ISR_RAMP_PEDGE)==0 );
		}
	}while(paramDataPrep->cycleNum != chirp_cnt);

	uint32_t ana_sta = ana_Venus_st->sys_sta0;
	RF_VENUS_DEINIT();
	BBE_OPGATE_DIS(BBE_GATE_PREP);//|BBE_GATE_P2|BBE_GATE_FFT);
	ANACFG_SET(&paramANA_Venus->ana1); //40M
	return  ((ana_sta>>6)&0x3);
}

// chirp间关闭晶振休眠 RTC+RC软延时 适用于较大chirp间隔应用
static uint32_t udsf_data_acquisiton_chirpsum_extreme_lpw(int predata_en,int alg0_en,int alg25_en,int chirp_addtion_intv_us)
{
	if( predata_en ){
		PREPDATA_HANDLE();
	}
	BBE_PREPINIT(paramDataPrep);    //bbe init, 2.9us
	RF_VENUS_INIT(); //4.9us
			
	uint32_t ana2_config0_rf_on   = paramANA_Venus->ana2.ana_cfg0;
	uint32_t ana2_config0_rf_off  = paramANA_Venus->ana2.ana_cfg0 & (~1);

	paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_off;
	ANACFG_SET(&paramANA_Venus->ana2);  // all on but rf

	paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_on;

	#if( TEST_MODE == 300 )
	paramDataPrep->cycleNum = 2;
	GPIO_OUTPUT_SET = 0;
	#endif
	
	ana_Venus_st->ramp_cmd        = VENUS_WAVE_START;       // sweep start

	BBE->ISR             = BBE_ISR_RAMP_PEDGE;	   // wair for wave0-B
	while( (BBE->ISR & BBE_ISR_RAMP_PEDGE)==0 );
	
	int chirp_cnt = 0;
	do{
		ANACFG_SET(&paramANA_Venus->ana2); // rf on
		// wait dataprep end
		BBE->OP_CLEAR=BBE_CLEAR_PREP;
		BBE_ISR_CLEAR(BBE_ISR_PREP_FRAME_END);// dataprep在wave0-A可能已采集满 add@230608
		BBE_WAITISR(BBE_ISR_PREP_FRAME_END);
		
		if( chirp_addtion_intv_us ){
			#if( TEST_MODE == 300 )
			GPIO_OUTPUT_SET = 1;
			#endif
			
			ana_Venus_st->ramp_cmd = VENUS_WAVE_STOP; 
			ANACFG_SET(&paramANA_Venus->ana1);
			BBE_OPGATE_DIS(BBE_GATE_PREP|BBE_GATE_P2|BBE_GATE_FFT|BBE_GATE_CFAR); // bbe opgate
			
			if( TEST_MODE == 600 ){
				while(1){
					WDT->STR = 1;
				}
			}
			// start a
			udsf_rtc_set(1,chirp_addtion_intv_us>>5);
		}else{
			ANACFG_SET(&paramANA_Venus->ana3); // rf if off
		}
		
		if( alg0_en ){
			P2_FFT_STEPCFG8_HANDLE((P2_FFT_CONFIG*)&paramALG->alg0,paramALG->alg0.dstInc*chirp_cnt);
		}

		if( alg25_en ){
			P2_FFT_STEPCFG8_HANDLE((P2_FFT_CONFIG*)&paramALG->alg25,paramALG->alg25.dstInc*chirp_cnt);
		}


		chirp_cnt++;
		
		if( paramDataPrep->cycleNum != chirp_cnt ){
			if( chirp_addtion_intv_us ){
				#if( TEST_MODE == 300 )
				GPIO_OUTPUT_SET = 0;
				#endif

				SYSC->CLK_EN &= (~BBE_EN_Msk); // bbe clk disable		
				
				if( TEST_MODE == 601 ){
					while(1){
						WDT->STR = 1;
					}
				}
				SYSC->CLK_SEL = BBE_ISO_SEL_MSK | LRC_SEL_MSK;// | LRC_DIV128_MSK; // 8K 
				ANACFG_SET(&paramANA_Venus->ana4); //40M // TODO 待优化

				#if( TEST_MODE == 300 )
				GPIO_OUTPUT_SET = 1;
				#endif
				// end a


				// start b
				if( TEST_MODE == 602 ){
					while(1){
						WDT->STR = 1;
					}
				}
				while ((RTC1->IRQ_CFG & 0x1ul) == 0); // wait rtc1 irq
				// end b

				#if( TEST_MODE == 300 )
				GPIO_OUTPUT_SET = 0;
				#endif
				// start c
				ANACFG_SET(&paramANA_Venus->ana1); //40M // TODO 待优化
				if( TEST_MODE == 603 ){ // 此处1.59mA
					while(1){
						WDT->STR = 1;
					}
				}
				udsf_slow_clk_delay500us();        //等待起振
				SYSC->CLK_SEL = 0;                 //40M
				// end c

				#if( TEST_MODE == 300 )
				GPIO_OUTPUT_SET = 1;
				#endif
				
				// start d
				RTC1->IRQ_CFG |= RTC_IRQ_MASK_Pos;    // rtc1 irq disable
				RTC1->IRQ_CFG |= RTC_IRQ_CLEAR_Msk;   // rtc1 irq flag clear
				SYSC->CLK_EN = SYSC->CLK_EN|BBE_EN_Msk&(~RTC1_PATTERN_SW_Msk);    // bbe_clk enable	
				SYSC->SWRST &= ~(1 << 11);  // bbe reset
				SYSC->SWRST |= (1 << 11);				
				BBE_OPGATE_DIS(BBE_GATE_PREP|BBE_GATE_P2|BBE_GATE_FFT|BBE_GATE_CFAR); // bbe opgate
				
				paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_off;
				ANACFG_SET(&paramANA_Venus->ana2);  // all on but rf
				paramANA_Venus->ana2.ana_cfg0 = ana2_config0_rf_on;
				BBE_PREPINIT(paramDataPrep);                     // bbe dp init, 2.9us
				RF_VENUS_INIT();                                 // ramp init,   4.9us

				ana_Venus_st->ramp_cmd = VENUS_WAVE_START;       // ramp start
				#if( TEST_MODE == 300 )
				GPIO_OUTPUT_SET = 0;
				#endif
				// end d
				
				if( TEST_MODE == 604 ){
					while(1){
						WDT->STR = 1;
					}
				}
			}
			
			BBE->ISR = BBE_ISR_RAMP_PEDGE;	     // wait for wave0-B
			while( (BBE->ISR & BBE_ISR_RAMP_PEDGE)==0 );
		}
	}while(paramDataPrep->cycleNum != chirp_cnt);

	uint32_t ana_sta = ana_Venus_st->sys_sta0;
	RF_VENUS_DEINIT();
	BBE_OPGATE_DIS(BBE_GATE_PREP);//|BBE_GATE_P2|BBE_GATE_FFT);
	ANACFG_SET(&paramANA_Venus->ana1); //40M
	return  ((ana_sta>>6)&0x3);
}

#endif
